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Altera/Mentor Graphics/Exemplar Logic Design Flow
The following figure shows the typical design flow for logic circuits created and processed with the MAX+PLUS
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| Last Updated: May 4, 2001 for MAX+PLUS II version 10.1 | |
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Copyright © 2001 Altera Corporation, 101 Innovation Drive, San Jose, California 95134, USA. All rights reserved. By accessing any information on this CD-ROM, you agree to be bound by the terms of Altera's Legal Notice. | |